Generally, a radio communication apparatus uses as a local oscillator circuit a frequency synthesizer using a PLL (Phase Locked Loop). FIG. 2 shows the configuration of a conventional frequency synthesizer using a PLL. As shown in FIG. 2, the frequency synthesizer comprises a quartz oscillator circuit 1, a reference frequency divider 2, a phase comparator 3, a charge pump circuit 4, a low pass filter (LPF) 5, a voltage-controlled oscillator (VCO) 6 and a variable frequency divider 7.
The quartz oscillator circuit 1 generates signals of a prescribed frequency. The reference frequency divider 2 divides the frequency of signals outputted from the quartz oscillator circuit 1 in a fixed dividing ratio to generate the reference signal of the reference frequency. The phase comparator 3 detects the phase difference between the reference signal outputted from the reference frequency divider 2 and the feedback signal outputted from the variable frequency divider 7, according to the result and outputs signals of logic “L” or “H” from an Up terminal and a Down terminal. The charge pump circuit 4, by performing a charging action or a discharging action on the basis of the signals outputted from the Up terminal and the Down terminal of the phase comparator 3, outputs a signal proportional to the phase difference detected by the phase comparator 3.
The LPF 5 clears the signal outputted from the charge pump circuit 4 of the high frequency component, and outputs the cleared signal to the VCO 6. The VCO 6 oscillates at a frequency proportional to the voltage of the signal outputted from the LPF 5, outputs the resultant signal to outside the frequency synthesizer as a local oscillation signal, and also outputs it to the variable frequency divider 7. The variable frequency divider 7 divides the output frequency of the VCO 4 in a designated dividing ratio, and feeds back the result to the phase comparator 3 as a feedback signal.
Next, the operation of the conventional frequency synthesizer configured in this way will be described. The phase comparator 3 detects the phase difference between the reference signal outputted from the reference frequency divider 2 and the feedback signal outputted from the variable frequency divider 7. If the phase of the feedback signal is behind the phase of the reference signal, a signal of logic “L” having a pulse width matching that phase difference is outputted from the Up terminal of the phase comparator 3. To the Down terminal of the phase comparator 3 then, a signal of logic “H” is outputted.
On the other hand, if the phase of the feedback signal is ahead of the phase of the reference signal, a signal of logic “L” having a pulse width matching that phase difference is outputted from the Down terminal of the phase comparator 3. To the Up terminal of the phase comparator 3 then, a signal of logic “H” is outputted. If the phase of the feedback signal is synchronous with the phase of the reference signal, signals of logic “H” are outputted from the Up terminal and the Down terminal of the phase comparator 3.
The charge pump circuit 4 comprises transistors (switching elements) to whose gates the Up terminal and the Down terminal of the phase comparator 3 are connected and a constant current source circuit connected to each transistor. If it receives a signal of logic “L” from the Up terminal of the phase comparator 3, it acts to charge itself by using a constant current source. Or if it receives a signal of logic “L” from the Down terminal of the phase comparator 3, it acts to discharge itself by using a constant current source.
When the output terminal voltage is raised by a charging action by the charge pump circuit 4, the oscillation frequency of the VCO 6 rises. On the other hand, when the output terminal voltage is lowered by a discharging action by the charge pump circuit 4, the oscillation frequency of the VCO 6 falls. The local oscillation signal outputted from the VCO 6 is fed back to the phase comparator 3 via the variable frequency divider 7.
If the frequency of the feedback signal is lower than the frequency of the reference signal (if the phase of the feedback signal is behind the phase of the reference signal), the output frequency of the VCO 6 rises as stated above, accordingly the frequency of the feedback signal rises, and the phase difference from the reference signal narrows. This brings the frequency of the local oscillation signal outputted from the VCO 6 close to a desired frequency which is proportional to the frequency of the reference signal.
Or if the frequency of the feedback signal is higher than the frequency of the reference signal (if the phase of the feedback signal is ahead of the phase of the reference signal), the output frequency of the VCO 6 falls as stated above, accordingly the frequency of feedback signal falls, and the phase difference from the reference signal narrows. This brings the frequency of the local oscillation signal outputted from the VCO 6 close to the desired frequency which is proportional to the frequency of the reference signal.
In this way, the frequency synthesizer so operates as to eventually bring the frequency of the feedback signal closer to the frequency of the reference signal no matter whether the frequency of the feedback signal (a frequency proportional to the output frequency of the VCO 6) is higher or lower than the frequency of the reference signal, and the oscillation frequency of the VCO 6 is locked to a fixed frequency. The signals outputted from the phase comparator 3 when in this locked state are supposed to be signals of logic “H” both from the Up terminal and the Down terminal.
So far, attempts have been made to reduce power consumption in frequency synthesizers configured in this way, and a number of techniques have been proposed (see Patent Documents 1 and 2 for instance).
Patent Document 1: Japanese Patent Laid-Open No. 10-224212 Patent Document 2: Japanese Patent Laid-Open No. 6-284069
By the technique described in Patent Document 1, a phase comparator is provided with a power-cut input terminal, and a charge pump circuit is placed in a high impedance state (floating state) by forcibly raising the signals outputted from the Down terminal and the Up terminal of the phase comparator to logic “H” when a power-cut signal is inputted, and the current flowing therein to a transistor is thereby eliminated.
Or by the technique described in Patent Document 2, when intermittent signals during waiting are turned off, the actions of a reference frequency divider, a variable frequency divider and a pre-scaler are stopped to achieve a lower current consumption state, a charge pump circuit is placed in a high impedance state, and its output voltage is held at the level when the frequency synthesizer is locked.